
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   19:11:29 03/03/2012
-- Design Name:   ST
-- Module Name:   C:/Users/Sebas/Desktop/proyectoAIC/processor-aic-ceu-11-12/tb_ST.vhd
-- Project Name:  Procesador
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ST
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_arith.all;

ENTITY tb_ST_vhd IS
END tb_ST_vhd;

ARCHITECTURE behavior OF tb_ST_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT ST
	PORT(
		clk : IN std_logic;
		clr : IN std_logic;
		st_sel : IN std_logic;
		st_en : IN std_logic;
		st_in : IN std_logic_vector(9 downto 0);          
		st_out : OUT std_logic_vector(9 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL clr :  std_logic := '0';
	SIGNAL st_sel :  std_logic := '0';
	SIGNAL st_en :  std_logic := '0';
	SIGNAL st_in :  std_logic_vector(9 downto 0) := (others=>'0');

	--Outputs
	SIGNAL st_out :  std_logic_vector(9 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: ST PORT MAP(
		clk => clk,
		clr => clr,
		st_sel => st_sel,
		st_en => st_en,
		st_in => st_in,
		st_out => st_out
	);

	
	clk <= not clk after 25 ns; --periodo de 50 ns;

	tb : PROCESS
	BEGIN
		
			clr <= '1';
			st_en <='1';
			st_in <= conv_std_logic_vector(1,10);
			st_sel <= '0'; --APILO
						
		wait for 49 ns;
		   st_in <= conv_std_logic_vector(3,10);
			st_sel <= '0'; --APILO
		wait for 50 ns;
		   st_in <= conv_std_logic_vector(7,10);
			st_sel <= '0'; --APILO
		wait for 50 ns;
		   st_in <= conv_std_logic_vector(15,10);
			st_sel <= '0'; --APILO
		wait for 50 ns;
		   st_in <= conv_std_logic_vector(31,10);
			st_sel <= '0'; --APILO
		wait for 50 ns;
		   st_in <= conv_std_logic_vector(63,10);
			st_sel <= '0'; --APILO
		wait for 50 ns;
		   st_in <= conv_std_logic_vector(127,10);
			st_sel <= '0'; --APILO
		wait for 50 ns;
		   st_in <= conv_std_logic_vector(255,10);
			st_sel <= '0'; --APILO
		
		--con este siguiente me paso
		wait for 50 ns;
		   st_in <= conv_std_logic_vector(511,10);
			st_sel <= '0'; --APILO
		
		wait for 50 ns;
		
		
			st_sel <= '1'; -- DESAPILO											
				
		wait for 50 ns;
				
			assert (st_out = conv_std_logic_vector(511,10))
				report "Error al desapilar el primero"
				severity FAILURE;
	
		wait for 50 ns;
			assert (st_out = conv_std_logic_vector(255,10))
				report "Error al desapilar el segundo"
				severity FAILURE;
		
		wait for 50 ns;
			assert (st_out = conv_std_logic_vector(127,10))
				report "Error al desapilar el tercero"
				severity FAILURE;
		
		wait for 50 ns;
			assert (st_out = conv_std_logic_vector(63,10))
				report "Error al desapilar el cuarto"
				severity FAILURE;
		wait for 50 ns;
			assert (st_out = conv_std_logic_vector(31,10))
				report "Error al desapilar el quinto"
				severity FAILURE;
		wait for 50 ns;
			assert (st_out = conv_std_logic_vector(15,10))
				report "Error al desapilar el sexto"
				severity FAILURE;
		wait for 50 ns;
			assert (st_out = conv_std_logic_vector(7,10))
				report "Error al desapilar el septimo"
				severity FAILURE;
		wait for 50 ns;
			assert (st_out = conv_std_logic_vector(3,10))
				report "Error al desapilar el octavo"
				severity FAILURE;
		
		
		 report ("**********TESTS DE ST SUPERADOS**********")
		 severity NOTE;
		wait; -- will wait forever
	END PROCESS;

END;
